Transistor and method of forming the transistor so as to have reduced base resistance

ABSTRACT

Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance R b . Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.

BACKGROUND

1. Field of the Invention

The disclosed embodiments relate to transistors and, more particularly,to a transistor structure, such as a bipolar junction transistor (BJT)or a heterojunction bipolar transistor (HBT) structure, having asilicided extrinsic base for reduced base resistance and a method offorming the transistor structure

2. Description of the Related Art

Those skilled in the art will recognize that it is desirable in bipolarjunction transistors (BJTs) and in high performance heterojunctionbipolar transistors (HBTs) to have a relatively high transit frequencyf_(T) and maximum oscillation frequency F_(max). F_(max) is a functionof f_(T) and of parasitics, including parasitic resistances andparasitic capacitances. One exemplary parasitic resistance is baseresistance R_(b). Thus, it would be advantageous to provide a transistorstructure, such as a BJT or HBT structure, with reduced base resistanceR_(b) as well as a method for forming such a transistor structure.

SUMMARY

Disclosed herein are embodiments of a transistor structure, such as abipolar junction transistor (BJT) structure or heterojunction bipolartransistor (HBT) structure, having an extrinsic base with a top surfacethat is completely silicided for reduced base resistance R_(b).Specifically, the transistor structure can incorporate a metal silicidelayer that covers the top surface of the extrinsic base, including theportion of the extrinsic base that extends below the upper portion of aT-shaped emitter (i.e., including the portion of the extrinsic base thatis at the extrinsic base to intrinsic base link-up region). Oneexemplary technique for ensuring that the metal silicide layer coversthis portion of the extrinsic base requires tapering the upper portionof the emitter. Such tapering allows a sacrificial dielectric layerbelow the upper portion of the emitter to be completely removed duringprocessing, thereby exposing the portion of the extrinsic base below andallowing the metal layer required for silicidation to be depositedthereon. In one embodiment, this metal layer can be deposited using ahigh pressure sputtering technique to ensure that all exposed surfacesof the extrinsic base, even those below the upper portion of theemitter, are covered.

More particularly, disclosed herein are embodiments of a transistorstructure, such as a BJT structure or HBT structure. The transistorstructure can comprise an intrinsic base, an emitter, and a dielectricspacer. The intrinsic base can be on a substrate above a collector. Theemitter can be essentially T-shaped and positioned above the intrinsicbase. Specifically, the emitter can have a lower portion on a firstregion of the intrinsic base opposite the collector and can further havean upper portion, which is wider (i.e., can have a greater diameter)than the lower portion. The dielectric spacer can be positionedlaterally adjacent to the lower portion only of the emitter.

The transistor structure can further comprise an extrinsic base and ametal silicide layer. The extrinsic base can be above and immediatelyadjacent to a second region of the intrinsic base such that it ispositioned laterally immediately adjacent to the dielectric spaceropposite the lower portion of the emitter. The metal silicide layer cancover the top surface of the extrinsic base such that it is alsopositioned laterally immediately adjacent to the dielectric spaceropposite the lower portion of the emitter.

As mentioned above, the upper portion of the emitter can be wider (i.e.,can have greater diameter) than the lower portion (i.e., the emitter canbe essentially T-shaped). Thus, in the transistor structure describedabove, the upper portion of the emitter can extend laterally over thedielectric spacer and further over a section of the silicide layer,which is immediately adjacent to the dielectric spacer and which isabove the extrinsic base to intrinsic base link-up region. One exemplaryprocessing technique for ensuring that the metal silicide layer coversthe entire extrinsic base, including the portion of the extrinsic basebelow the upper portion of the emitter (i.e., including the portion ofthe extrinsic base at the extrinsic base to intrinsic base link-upregion), and for also ensuring that the upper portion of the emitter issufficiently large enough to receive an emitter contact requirestapering the upper portion of the emitter. Such tapering allows asacrificial dielectric layer on the extrinsic base to be removed duringprocessing, thereby exposing the entire top surface of the extrinsicbase and allowing the metal layer required for the silicidation to bedeposited thereon. Thus, in one embodiment of the transistor structure,the upper portion of the emitter has a top surface and a taperedsidewall. The tapered sidewall specifically tapers from the top surfacetoward the dielectric spacer such that the width (i.e., diameter) of theupper portion gradually decreases between the top surface and theinterface between the upper portion and the lower portion of theemitter.

Also disclosed herein are embodiments of a method of forming atransistor structure (e.g., a BJT structure or a HBT structure), asdescribed above. The method can comprise depositing a polysilicon layerand performing at least one etch process so as to create, from thepolysilicon layer, an essentially T-shaped emitter that comprises alower portion and an upper portion above the lower portion.Specifically, the polysilicon layer can be deposited and etched so thatthe lower portion of the emitter is on a first region of an intrinsicbase opposite a collector and is positioned laterally adjacent to adielectric spacer and so that the upper portion of the emitter is wider(i.e., has a greater diameter) than the lower portion and extendslaterally over the dielectric spacer onto a sacrificial dielectriclayer.

Next, the method can comprise selectively removing the sacrificialdielectric layer so as to expose the top surface of an extrinsic base.This extrinsic base can be above and immediately adjacent to a secondregion of the intrinsic base such that it is positioned laterallyimmediately adjacent to the dielectric spacer opposite the lower portionof the emitter.

After the sacrificial dielectric layer is removed, a metal silicidelayer can be formed on the top surface of the extrinsic base such thatthe metal silicide layer is positioned laterally immediately adjacent tothe dielectric spacer opposite the lower portion of the emitter (i.e.,at the extrinsic base to intrinsic base link-up region) and, therebysuch that a section of the metal silicide layer is below the upperportion of the emitter. Forming the metal silicide layer can comprisedepositing a metal layer onto the extrinsic base, performing asilicidation anneal and then removing any excess metal material. Itshould be noted that the metal layer deposition in this case cancomprise using a high pressure sputtering technique in order to ensurethat the metal layer is deposited below the upper portion of theemitter.

One exemplary processing technique for ensuring that the metal silicidelayer covers the entire top surface of the extrinsic base, including theportion of the extrinsic base immediately adjacent to the dielectricspacer (i.e., including the portion of the extrinsic base at theextrinsic base to intrinsic base link-up region) and for also ensuringthat the upper portion of the emitter is sufficiently large enough toreceive an emitter contact requires tapering the upper portion of theemitter. That is, during the etch process(es) described above, thepolysilicon layer can further be etched such that the upper portion ofthe emitter has a tapered sidewall. Specifically, the etch process(es)can be performed so that the resulting sidewall is tapered from the topsurface of the upper portion of the emitter toward the dielectric spacerand, thereby such that the width (i.e., diameter) of the upper portionof the emitter gradually decreases between the top surface and theinterface between the upper portion and the lower portion of theemitter. This tapered sidewall allows the portion of the sacrificialdielectric layer below the upper portion of the emitter to be easily andcompletely removed and further provides less obstructed access, formetal layer deposition, to the exposed portion of the extrinsic basebelow the upper portion of the emitter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The embodiments disclosed herein will be better understood from thefollowing detailed description with reference to the drawings, which arenot necessarily drawn to scale and in which:

FIG. 1 is a cross-section diagram illustrating an embodiment of atransistor structure;

FIG. 2A is a cross-section diagram illustrating an alternative shape fora tapered sidewall in the transistor of FIG. 1;

FIG. 2B is a cross-section diagram illustrating another alternativeshape for a tapered sidewall in the transistor of FIG. 1;

FIG. 3 is a flow diagram illustrating an embodiment of a method offorming a transistor structure;

FIG. 4 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 5 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 6 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 7 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 8 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 9 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 10 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 11 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 12 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 13 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3;

FIG. 14 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3; and

FIG. 15 is a cross-section diagram illustrating a partially completedtransistor structure formed according to the method of FIG. 3.

DETAILED DESCRIPTION

The disclosed embodiments and the various features and advantageousdetails thereof are explained more fully with reference to theaccompanying drawings and the following detailed description.

As mentioned above, it is desirable in bipolar junction transistors(BJTs) and in high performance heterojunction bipolar transistors (HBTs)to have a relatively high transit frequency f_(T) and maximumoscillation frequency F_(max). F_(max) is a function of f_(T) and ofparasitics, including parasitic resistances and parasitic capacitances.One exemplary parasitic resistance is base resistance R_(b). Thus, itwould be advantageous to provide a transistor structure, such as a BJTor HBT structure, with reduced base resistance R_(b) as well as a methodfor forming such a transistor structure. Oftentimes a silicide layer isformed on the extrinsic base of a BJT or HBT and the contacts to theextrinsic base land on the silicide layer. This silicide layer reducesbase resistance to some extent. However, it typically does not cover theentire top surface of the extrinsic base and, particularly, does notcover the portion of the extrinsic base that is below the upper portionof the emitter and closest to the emitter opening (i.e., does not coverthe portion of the extrinsic base that is at the extrinsic base tointrinsic base link-up region). Thus, it would be advantageous toprovide a transistor structure, such as a BJT structure or HBTstructure, with reduced base resistance R_(b) over prior art transistorstructures as well as a method for forming such a transistor structure.

In view of the foregoing, disclosed herein are embodiments of atransistor structure, such as a bipolar junction transistor (BJT)structure or heterojunction bipolar transistor (HBT) structure, havingan extrinsic base with a top surface that is completely silicided forreduced base resistance R_(b). Specifically, the transistor structurecan incorporate a metal silicide layer that covers the top surface ofthe extrinsic base, including the portion of the extrinsic base thatextends below the upper portion of a T-shaped emitter (i.e., includingthe portion of the extrinsic base that is at the extrinsic base tointrinsic base link-up region). One exemplary technique for ensuringthat the metal silicide layer covers this portion of the extrinsic baserequires tapering the upper portion of the emitter. Such tapering allowsa sacrificial dielectric layer below the upper portion of the emitter tobe completely removed during processing, thereby exposing the portion ofthe extrinsic base below and allowing the metal layer required forsilicidation to be deposited thereon. In one embodiment, this metallayer can be deposited using a high pressure sputtering technique toensure that all exposed surfaces of the extrinsic base, even those belowthe upper portion of the emitter, are covered.

More particularly, referring to FIG. 1, disclosed herein are embodimentsof a transistor structure 100, such as a BJT structure or HBT structure.This transistor structure 100 can comprise a semiconductor substrate 101having a first type conductivity (e.g., P-type). For example, thesemiconductor substrate 101 can comprise a P− silicon substrate (i.e., asilicon substrate that is lightly doped with a P-type dopant). Forillustration purposes, the substrate 101 is shown as a bulksemiconductor substrate. However, it should be understood that thesubstrate 101 can, alternatively, comprise a semiconductor layer of asemiconductor-on-insulator wafer.

The transistor structure 100 can further comprise a collector 110 withinthe substrate 101. This collector region 110 can have a second typeconductivity (e.g., N-type) that is different from the first typeconductivity. Various different configurations for BJT and HBTcollectors are well-known in the art and could be incorporated into thetransistor structure 100. For example, the collector 110 can comprise asingle N-well region. Alternatively, the collector 110 can comprisemultiple N-type collector components, such as the following componentsdescribed and illustrated in U.S. Patent Publication No. 2008/0265282 ofGluschenkov et al., published on Oct. 30, 2008, assigned toInternational Business Machines Corporation, and incorporated herein byreference: an N+ buried collector within the substrate; an N− collectorabove the N+ buried collector and extending to the top surface of thesubstrate; and an N+ selective implant collector (SIC) pedestal withinthe N− collector immediately adjacent to the N+ buried collector andseparated from the top surface of the substrate by some distance.

Optionally, the transistor structure 100 can further comprise a shallowtrench isolation (STI) region positioned within and at the top surfaceof the semiconductor substrate 101 so as to define the active area ofthe transistor 100. Specifically, this STI region 102 can, for example,comprise a relatively shallow trench patterned and etched into the topsurface of the substrate 101 around (i.e., bordering) an area designatedas the active area of the transistor 100. The trench can be filled withone or more isolation materials (e.g., silicon dioxide (SiO₂), siliconnitride (SiN), silicon oxynitride (SiON) or any other suitable isolationmaterial or combination thereof).

An intrinsic base 103 can be positioned on the semiconductor substrate101 over the collector 110 and, optionally, extending laterally over theSTI region 102. The intrinsic base 103 can comprise an epitaxialsemiconductor layer and, thus, will generally comprise a singlecrystalline semiconductor material over the substrate 101 and apolycrystalline semiconductor material over the STI regions 102. In thecase of a BJT structure, the intrinsic base 103 can comprise, forexample, an epitaxial silicon layer. In the case of a HBT structure, theintrinsic base 103 can comprise, for example, an epitaxial silicongermanium layer.

The transistor structure 100 can further comprise an essentiallyT-shaped emitter 150 above the intrinsic base 103 and a dielectricspacer 111 positioned laterally adjacent to a lower portion 151 of theT-shaped emitter 150. Specifically, the emitter 150 can have a lowerportion 151 that is positioned above a first region 103 a of theintrinsic base 103 opposite the collector 110 and that is furtherpositioned laterally adjacent to the dielectric spacer 111. The emitter150 can further have an upper portion 152, which is above and wider thanthe lower portion 151. The geometry of the wider upper portion 151 canbe defined by an etch process (see the detailed discussion regarding theformation of the upper portion 151 of the emitter 150 as set out in thedescription of the method embodiments below) and can be designedspecifically to provide a sufficiently large surface area for receivingan emitter contact 190, given current state of the art lithographicpatterning techniques for forming contact openings. The geometry of thenarrower lower portion 151 can be essentially defined by the size andshape of an emitter opening as well as the dielectric spacer 111contained therein (see the detailed discussion regarding the formationof the lower portion 151 of the emitter 150 as set out in thedescription of the method embodiments below) and can specifically bedesigned to achieve a given area ratio between the emitter 150 and theintrinsic base 103. In an exemplary embodiment, the lower portion 151 ofthe emitter 150 surrounded by the dielectric spacer 111 can have a width(i.e., a diameter) ranging anywhere from 60 nm to 300 nm, while theupper portion 152 of the emitter (as measured at the top surface 153)can have a width (i.e., a diameter) ranging anywhere from 200 nm to 600nm. The emitter 150 can comprise, for example, a polysilicon layerhaving the same second type conductivity as the collector region (e.g.,N-type). The dielectric spacer 111 can comprise a sidewall spacer formedon the sidewall of an emitter opening (see the detailed discussionregarding the formation of the dielectric spacer 111 as set out in thedescription of the method embodiment below) and can comprise adielectric material, such as silicon nitride (SiN), silicon oxynitride(SiON) or any other suitable dielectric material.

The transistor structure 100 can further comprise a raised extrinsicbase 108. This raised extrinsic base 108 can be above and immediatelyadjacent to a second region 103 b of the intrinsic base 103, therebycreating an extrinsic base to intrinsic base link-up region 106. Thus,the raised extrinsic base 108 is positioned laterally immediatelyadjacent to the dielectric spacer 111 opposite the lower portion 151 ofthe emitter 150. The raised extrinsic base 108 can further extendlaterally over at least one isolation layer (e.g., a silicon dioxide(SiO₂) layer 104-polysilicon layer 105 stack). The stack of isolationlayer(s) 104, 105 can be positioned on a third region 103 c of theintrinsic base 103 (e.g., above the STI region 102). The raisedextrinsic base 108 can comprise an epitaxial semiconductor layer (e.g.,an epitaxial silicon layer) and can have the first type conductivity(e.g., P-type). Those skilled in the art will recognize that, due to theepitaxial growth process used to form the extrinsic base, thecrystalline structure of the raised extrinsic base 108 may vary. Forexample, the portion of the extrinsic base 108 at the extrinsic base tointrinsic base link-up region may be single crystalline silicon and theportion of the extrinsic base 108 above the stack of isolation layer(s)104, 105 may be polycrystalline silicon. Additionally, those skilled inthe art will recognize that the concentration of dopant (e.g., P-typedopant) in the extrinsic base 108 will typically be relatively high ascompared to the concentration of dopant in the intrinsic base 103.

The transistor structure 100 can further comprise metal silicidelayer(s) 120, at least one dielectric layer 130 on the metal silicidelayer(s) 120 and a plurality of contacts 190 that extend through thedielectric layer 130 to the metal silicide layer(s) 120. Specifically, ametal silicide layer 120 can cover the top surface 118 of the extrinsicbase 108 such that it is positioned laterally immediately adjacent tothe dielectric spacer 111 opposite the lower portion 151 of the emitter150. Thus, this metal silicide layer 120 will be above the extrinsicbase 108 at the extrinsic base to intrinsic base link-up region 106.Optionally, a metal silicide layer 120 can also cover the top surface153 of the upper portion 152 of the emitter 150. These metal silicidelayers 120 can each comprise a silicide of, for example, a refractory ornoble metal (e.g., nickel (Ni), cobalt (Co), tungsten (W), chromium(Cr), platinum (Pt), titanium (Ti), molybdenum (Mo), palladium (Pd),etc.) or an alloy thereof. The dielectric layer(s) 130 can comprise anyone or more interlayer dielectrics, such as, silicon dioxide (SiO₂),silicon nitride (SiN), borophosphosilicate glass (BPSG), etc. At least aportion of the dielectric layer(s) 130 can be positioned laterallyadjacent to the dielectric spacer 111 opposite the lower portion 151 ofthe emitter 150 and further positioned vertically between the metalsilicide layer 120 and the tapered sidewall 154 of the upper portion 152of the emitter. Contacts 190 can extend vertically through thedielectric layer(s) 130 to the metal silicide layer(s) 120 in order tocontact the extrinsic base 108, the emitter 150, etc.

As mentioned above, the upper portion 152 of the emitter 150 can bewider (i.e., can have a greater diameter) than the lower portion 151(i.e., the emitter 150 can be essentially T-shaped). Thus, in thetransistor structure 100 described above, the upper portion 150 of theemitter 150 can extend laterally over the dielectric spacer 111 andfurther over that section 121 of the metal silicide layer 120, which isimmediately adjacent to the dielectric spacer 111 and which is above theextrinsic base to intrinsic base link-up region 106. One exemplaryprocessing technique for ensuring that the metal silicide layer 120covers the entire extrinsic base 108, including the portion of theextrinsic base 108 below the upper portion 152 of the emitter 150 (i.e.,including the portion of the extrinsic base 108 at the extrinsic base tointrinsic base link-up region 106), and for also ensuring that the upperportion 152 of the emitter 150 is sufficiently large enough to receivean emitter contact 190 requires tapering the upper portion 152 of theemitter 150. Such tapering allows a sacrificial dielectric layer on theextrinsic base to be removed during processing, thereby exposing theentire top surface of the extrinsic base and allowing the metal layerrequired for the silicidation to be deposited thereon.

Therefore, in one embodiment of the transistor structure 100, the upperportion 151 of the emitter 150 has a top surface 153 and a taperedsidewall 154. The tapered sidewall 154 can specifically taper from thetop surface 153 toward the dielectric spacer 111 such that the width(i.e., diameter) of the upper portion 152 gradually decreases betweenthe top surface 153 and the interface 156 between the upper portion 152and the lower portion 151 of the emitter 150. In an exemplaryembodiment, the width (i.e., diameter) of the upper portion 152 of theemitter 150 can gradually decrease from approximately 440 nm toapproximately 240 nm. To achieve this gradual decrease in width (i.e.,in diameter), various different etch process may be used (as discussedin detail below with regard to the method embodiments). Thus, in theresulting structure, the tapered sidewall 154 may be linear (as shown inFIG. 1), curved (as shown in FIGS. 2A and 2B), stepped or may have anyother suitable shape. In any case, the taper angle 155 (i.e., the anglebetween the top surface 153 of the emitter 150 and the sidewall 154) canrange between 30 and 75 degrees (e.g., approximately 45 degrees). Theshape (i.e., linear, curved, stepped, etc.) of the tapered sidewall 151and the taper angle 155 can be defined by the etch processes used andcan be designed so that, during processing, a sacrificial dielectriclayer on the extrinsic base 108 can be completely removed, therebyexposing the all or essentially all of the top surface of the extrinsicbase 108, including the portion of the extrinsic base 108 below theupper portion 152 of the emitter 150 (i.e., including the portion of theextrinsic base 108 at the extrinsic base to intrinsic base link-upregion 106) and allowing a metal layer required for silicidation to bedeposited thereon (see the detailed discussion regarding the taperingetch processes as set out in the description of the method embodimentsbelow).

It should also be understood that in the transistor structureembodiments, described in detail above, any N-type component willcomprise (e.g., will be doped with, implanted with, etc.) an N-typedopant and any P-type component will comprise (e.g., will be doped with,implanted with, etc.) a P-type dopant. Such N-type dopants can comprise,for example, Group V dopants, such as arsenic (As), phosphorous (P) orantimony (Sb) and such P-type dopants can comprise, for example, GroupIII dopants, such as boron (B) or indium (In)).

Referring to FIG. 3, also disclosed herein are embodiments of a methodof forming a transistor structure 100 (e.g., a BJT structure or a HBTstructure), as described above, and illustrated in FIG. 1. The methodcan comprise providing a semiconductor substrate 101 having a first typeconductivity (e.g., P-type) (302). For example, the semiconductorsubstrate 101 can comprise a P− silicon substrate (i.e., a siliconsubstrate lightly doped with a P-type dopant). For illustrationpurposes, the substrate 101 is shown as a bulk semiconductor substrate.However, it should be understood that the substrate 101 can,alternatively comprise a semiconductor layer of asemiconductor-on-insulator wafer.

Optionally, a shallow trench isolation (STI) region 102 can be formedwithin and at the top surface of the semiconductor substrate 101 so asto define the active area of the transistor 100 (304, see FIG. 4). TheSTI region 102 can be formed using conventional shallow trench isolation(STI) formation techniques. For example, a trench can belithographically patterned and etched into the semiconductor substrate101 so as to define the active region. The trench can then be filledwith one or more isolation materials (e.g., silicon oxide (SiO₂),silicon nitride (SiN), silicon oxynitride (SiON) or any other suitableisolation materials).

Additionally, a collector 110 can be formed within the semiconductorsubstrate 101 (304, see FIG. 4). This collector 110 can be formed so asto have a second type conductivity (e.g., N-type) that is different fromthe first type conductivity. Various different techniques for formingBJT and HBT collectors are well-known in the art and can be incorporatedinto the method embodiments disclosed herein. For example, the collector110 can be formed as a single N-well region. Alternatively, thecollector 110 can be formed as multiple N-type collector components,such as the following components described and illustrated in U.S.Patent Publication No. 2008/0265282 of Gluschenkov et al., published onOct. 30, 2008, assigned to International Business Machines Corporation,and incorporated herein by reference: an N+ buried collector within thesubstrate; a N− collector above the N+ buried collector and extending tothe top surface of the substrate; and an N+ selective implant collector(SIC) pedestal within the N− collector immediately adjacent to the N+buried collector and separated from the top surface of the substrate bysome distance.

After the STI region 102 and collector 110 are formed, an intrinsic base103 can be formed on the semiconductor substrate 101 (306, see FIG. 5).Specifically, a first epitaxial semiconductor layer (e.g., an epitaxialsilicon layer in the case of a BJT structure or an epitaxial silicongermanium layer in the case of an HBT structure) having a predeterminedthickness (e.g., 0.01-0.2 μm) can be formed using a conventionalepitaxial growth process (e.g., an ultra high-vacuum/chemical vapordeposition (UHV/CVD) low-temperature epitaxy (LTE) process). As aresult, the intrinsic base 103 will generally comprise a singlecrystalline semiconductor material over the semiconductor substrate 101and a polycrystalline semiconductor material over the STI region 102.The intrinsic base 103 is preferably in-situ doped with a first typeconductivity dopant (e.g., a P-type dopant) such that it has the firsttype conductivity (e.g., P-type).

Once the intrinsic base 103 is formed, a silicon dioxide (SiO₂) layer104 that is approximately 5-20 nm thick can be deposited on theintrinsic base 103 and a first polysilicon layer 105 that isapproximately 20-100 nm thick can be deposited on the SiO₂ layer 104(308, see FIG. 6). Next, an opening 109 for an extrinsic base tointrinsic base link-up region can be formed in the layers 104, 105,thereby also creating an emitter opening landing pad 107 (310, see FIG.7). For example, a photoresist layer can be formed on the firstpolysilicon layer 105 and lithographically patterned for the opening109. The first polysilicon layer 105 can then be anisotropically etchedstopping on the SiO₂ layer 104. The photoresist layer can then beremoved and chemical oxide removal (COR) process can be performed so asto remove exposed portions of the SiO₂ layer 104 within the opening 109with minimal undercut.

Then, a second epitaxial semiconductor layer for a raised extrinsic base108 can be formed (e.g., by low-temperature epitaxy (LTE)) on the firstpolysilicon layer 105 and further on the exposed region 103 b of theintrinsic base 103 in the opening 109, thereby creating the extrinsicbase to intrinsic base link-up region 106 (312, see FIG. 8). Thoseskilled in the art will recognize that, due to the epitaxial growthprocess used at process 312, the crystalline structure of the resultingextrinsic base 108 may vary. For example, the portion of the extrinsicbase 108 at the extrinsic base to intrinsic base link-up region 106 maybe single crystalline silicon and the portion of the extrinsic base 108above the polysilicon layer 105 may be polycrystalline silicon. Thisepitaxial semiconductor layer can be either in situ doped orsubsequently implanted with a first type conductivity dopant (e.g., aP-type dopant) so that it has the first type conductivity (e.g.,P-type). Typically, the extrinsic base 108 will be doped with arelatively high concentration of the dopant as compared to the intrinsicbase 103.

After the second epitaxial semiconductor layer for the raised extrinsicbase 108 is formed, a blanket sacrificial dielectric layer 112 with athickness greater than approximately 50 nm can be deposited onto thesecond polysilicon layer (314, see FIG. 8). This sacrificial dielectriclayer 112 can comprise, for example, silicon dioxide (SiO₂) or any othersuitable dielectric material that can be selectively etched over thedielectric spacer that will subsequently be formed at process 318,discussed below. Then, an emitter opening 113 can be formed (316, seeFIG. 9). Specifically, conventional lithographic patterning and etchtechniques can be used to form an opening 113 that extends verticallythrough the sacrificial dielectric layer 112, through the secondepitaxial semiconductor layer (i.e., through the extrinsic base 108),and through the first polysilicon layer 105 to the oxide layer 104 ofthe emitter opening landing pad 107.

Once the emitter opening 113 is formed, a dielectric spacer 111 can beformed on the sidewall of the opening 113 such that it is positionedlaterally immediately adjacent to vertical surfaces of the sacrificialdielectric layer 112 and the extrinsic base 108 (318, see FIG. 10). Thedielectric spacer 111 can be formed using conventional sidewall spacerformation techniques. For example, a conformal layer of dielectricmaterial (e.g., silicon nitride (SiN) or any other material that willremain essentially intact during subsequent removal of the sacrificialdielectric layer 112 at process 328, discussed below) can be depositedand then anisotropically etched so as to remove it from any horizontalsurfaces. Next, the portion of the oxide layer 104 exposed at the bottomof the emitter opening 113 can be removed (e.g., by a chemical oxideremoval (COR) process), thereby exposing a first region 103 a of theintrinsic base 103 (320, see FIG. 11).

Then, a second polysilicon layer 140 for the emitter 150 can bedeposited on top of the sacrificial dielectric layer 112 so as to fillthe emitter opening 113 (322, see FIG. 12). This second polysiliconlayer can be either in-situ doped or subsequently implanted with asecond type conductivity dopant (e.g., an N-type dopant) such that ithas the same conductivity type as the collector 110. Next, at least oneetch process can be performed so as to create, from the secondpolysilicon layer, an essentially T-shaped emitter 150 that comprises alower portion 151 and an upper portion 152 above the lower portion 151(324, see FIG. 13). Specifically, a mask that is wider than the emitteropening 113 can be formed on the second polysilicon layer aligned abovethe emitter opening 113. The lower portion 151 of the emitter 150 can bethat portion of the second polysilicon layer within the emitter opening113 on the first region 103 a of the intrinsic base 103 opposite thecollector 110 and further positioned laterally adjacent to thedielectric spacer 111. Thus, the geometry of the lower portion 151 canbe essentially defined by the size and shape of an emitter opening 113as well as the dielectric spacer 111 contained therein and canspecifically be designed to achieve a given area ratio between theemitter 150 and the intrinsic base 103. In an exemplary embodiment, thelower portion 151 of the can have a width (i.e., a diameter) ranginganywhere from 60 nm to 300 nm. Using the mask, one or more etchprocess(es) can be performed so as to define the size and shape of theupper portion 152 of the emitter 150 so that the upper portion 152 iswider than the lower portion 151 and so that it extends laterally overthe dielectric spacer 111 onto the sacrificial dielectric layer 112. Thewider upper portion 152 is designed to provide a sufficiently largesurface area for subsequently receiving an emitter contact 190 atprocess 332, discussed below, given current state of the artlithographic patterning techniques for forming contact openings. In oneexemplary embodiment, the etch process(es) can be performed so that theupper portion 152 of the emitter (as measured at the top surface 153)has a diameter ranging anywhere from 200 nm to 600 nm.

Next, the method can comprise selectively removing the sacrificialdielectric layer 112 (326, see FIG. 14). The sacrificial dielectriclayer 112 is removed at process 326 so as to expose essentially theentire top surface 118 of the extrinsic base 108, including the portionof the extrinsic base 108 that is below the upper portion 152 of theemitter 150 at the extrinsic base to intrinsic base link-up region 106(i.e., including the portion of the extrinsic base 108 immediatelyadjacent to the second region 103 b of the intrinsic base 103). Thesacrificial dielectric layer 112 can be removed, for example, using aselective isotropic wet chemical etch (e.g., diluted HF or buffered HF)so as to ensure that the extrinsic base 108 and dielectric spacer 111remain intact.

After the sacrificial dielectric layer 112 is removed, a metal silicidelayer 120 can be formed on the top surface 118 of the extrinsic base 108such that the metal silicide layer 120 is positioned laterallyimmediately adjacent to the dielectric spacer 111 opposite the lowerportion 151 of the emitter 150 (i.e., at the extrinsic base to intrinsicbase link-up region 106) and, thus, such that a section 121 of the metalsilicide layer 120 is below the upper portion 152 of the emitter 150(328, see FIG. 15). Optionally, a metal silicide layer 120 can alsoessentially simultaneously be formed on the top surface 153 of the upperportion of the emitter 150. Forming the metal silicide layer 120 cancomprise depositing a metal layer on the extrinsic base. This metallayer can, for example, comprise a refractory or noble metal (e.g.,nickel (Ni), cobalt (Co), tungsten (W), chromium (Cr), platinum (Pt),titanium (Ti), molybdenum (Mo), palladium (Pd), etc.) or an alloythereof. In one embodiment, the metal layer can be deposited using ahigh pressure sputtering technique in order to ensure that the metallayer is deposited below the upper portion of the emitter. For example,the metal layer can be sputtered onto the top surface 118 of theextrinsic base 108 under the following conditions: pressure of at least0.5 mTorr (e.g., 0.5-50 mTorr or more, and, preferably, at approximately20 mTorr), power at 0.02-3 kW, radio frequency (RF) bias on the wafer of0-1 kW (and, preferably, at a RF bias of at least 5 Watts) andtemperature at 15-300° C. After the metal layer is deposited, asilicidation anneal (e.g., a thermal anneal) can be performed in orderto cause metal atoms from the metal layer to react with the siliconmaterial below and, thereby create the metal silicide layers 120 at themetal-silicon interfaces. Finally, any excess unreacted metal can beselectively removed.

One exemplary processing technique for ensuring that a metal silicidelayer 120 covers the entire top surface 118 of the extrinsic base 108,including the portion of the extrinsic base immediately adjacent to thedielectric spacer 111 (i.e., including the portion of the extrinsic baseat the extrinsic base to intrinsic base link-up region 106) and for alsoensuring that the upper portion 152 of the emitter 150 is sufficientlylarge enough to receive an emitter contact requires tapering the upperportion of the emitter. That is, during the etch process(es) 324discussed above, the second polysilicon layer can further be etched suchthat the upper portion 152 of the emitter 150 has a tapered sidewall 154(see FIG. 13). Specifically, the etch process(es) 324 can be performedso that that the resulting sidewall 154 is tapered from the top surface153 of the upper portion 152 of the emitter 150 toward the dielectricspacer 111 and, thereby such that the width (i.e., diameter) of theupper portion 152 of the emitter 150 gradually decreases between the topsurface 153 and the interface 156 between the upper portion 152 and thelower portion 151 of the emitter 150. In an exemplary embodiment, theetch process(es) 324 can be performed such that the width (i.e., thediameter) of the upper portion 152 of the emitter 150 graduallydecreases from approximately 440 nm to approximately 240 nm.

Depending upon the etch process(es) 324 used, the shape of the taperedsidewall 154 may vary. For example, a tapered sidewall 154 that islinear (as shown in FIG. 1) may be achieved by using SF6 etch undercontrolled constant pressure conditions. In this case, the angle of etchis dependent on incoming etch film thickness. As etch film thicknessdecreases, the range of achievable angles diminishes. Alternatively, atapered sidewall that is curved (as shown in FIGS. 2A and 2B) may beachieved by achieved through dynamic control of etch pressure settings.Gradual increase or decrease of pressure determines curvature of etchprofile. It should be understood that the varying shapes of the taperedsidewall 154, as shown FIGS. 1, 2A and 2B are not intended to belimiting. Other etch process(es) that result in other shapes (e.g.stepped, etc.) could alternatively be used. In any case, the etchprocess(es) 324 should be performed so that the taper angle 155 (i.e.,the angle between the top surface 153 of the emitter 150 and thesidewall 154) ranges between 30 and 75 degrees (e.g., is approximately45 degrees) and specifically so that, at process 326, the sacrificialdielectric layer 112 on the extrinsic base 108 can be easily andessentially completely removed and so that, as process 328, there isless obstructed access, for metal layer deposition, to the exposedportion of the extrinsic base 108 below the upper portion 152 of theemitter 150.

Following silicide layer formation, additional process steps can beperformed in order to complete the transistor structure 100 (330-332,see FIG. 1). For example, one or more dielectric layer(s) 130 can beformed (e.g., deposited using conventional techniques) onto the metalsilicide layer(s) 120. Specifically, the dielectric layer(s) 130 can bedeposited such that at least a portion of a dielectric layer ispositioned laterally adjacent to the dielectric spacer 111 opposite thelower portion 151 of the emitter 150 and further positioned verticallybetween the metal silicide layer 120 and the tapered sidewall 154 of theupper portion 152 of the emitter 150. The dielectric layer(s) 130 cancomprise any one or more interlayer dielectrics, such as, silicondioxide (SiO₂), silicon nitride (SiN), borophosphosilicate glass (BPSG),etc. Additionally, conventional processing techniques can be used toform contacts 190 that extend vertically through the dielectric layer(s)130 to the metal silicide layer(s) 120 in order to contact the extrinsicbase 108, the emitter 150, etc.

The method embodiments as described can be used in the fabrication ofintegrated circuit chips. The resulting integrated circuit chips can bedistributed by the fabricator in raw wafer form (that is, as a singlewafer that has multiple unpackaged chips), as a bare die, or in apackaged form. In the latter case the chip is mounted in a single chippackage (such as a plastic carrier, with leads that are affixed to amotherboard or other higher level carrier) or in a multichip package(such as a ceramic carrier that has either or both surfaceinterconnections or buried interconnections). In any case the chip isthen integrated with other chips, discrete circuit elements, and/orother signal processing devices as part of either (a) an intermediateproduct, such as a motherboard, or (b) an end product. The end productcan be any product that includes integrated circuit chips, ranging fromtoys and other low-end applications to advanced computer products havinga display, a keyboard or other input device, and a central processor.

It should be understood that the terminology used herein is for thepurpose of describing the disclosed embodiments and is not intended tobe limiting. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It should further be understood that the terms“comprises” “comprising”, “includes” and/or “including”, as used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof. Additionally,it should be understood that the corresponding structures, materials,acts, and equivalents of all means or step plus function elements in theclaims below are intended to include any structure, material, or act forperforming the function in combination with other claimed elements asspecifically claimed. The details set for above have been presented forpurposes of illustration and description and are not intended to beexhaustive or limiting. Many modifications and variations to thedisclosed embodiments will be apparent to those of ordinary skill in theart without departing from the scope and spirit thereof. The detailswere provided in order to best explain the principles and practicalapplication of the embodiments and to enable others of ordinary skill inthe art to understand the embodiments with various modifications as aresuited to the particular use contemplated.

Therefore, disclosed above are embodiments of a transistor structure,such as a bipolar junction transistor (BJT) structure or aheterojunction bipolar transistor (HBT) structure, having an extrinsicbase with a top surface that is completely silicided for reduced baseresistance R_(b). Specifically, the transistor structure can incorporatea metal silicide layer that covers the top surface of the extrinsicbase, including the portion of the extrinsic base that extends below theupper portion of a T-shaped emitter (i.e., including the portion of theextrinsic base that is at the extrinsic base to intrinsic base link-upregion). One exemplary technique for ensuring that the metal silicidelayer covers this portion of the extrinsic base requires tapering theupper portion of the emitter. Such tapering allows a sacrificialdielectric layer below the upper portion of the emitter to be completelyremoved during processing, thereby exposing the portion of the extrinsicbase below and allowing the metal layer required for silicidation to bedeposited thereon. In one embodiment, this metal layer can be depositedusing a high pressure sputtering technique to ensure that all exposedsurfaces of the extrinsic base, even those below the upper portion ofthe emitter, are covered.

1. A transistor comprising: an intrinsic base; an emitter on saidintrinsic base, said emitter comprising: a lower portion; and an upperportion above said lower portion; a dielectric spacer positionedlaterally adjacent to said lower portion; an extrinsic base above saidintrinsic base and positioned laterally adjacent to said dielectricspacer opposite said lower portion; and a silicide layer on saidextrinsic base and positioned laterally adjacent to said dielectricspacer opposite said lower portion, said upper portion being wider thansaid lower portion and extending laterally over said dielectric spacerand a section of said silicide layer.
 2. The transistor of claim 1,further comprising: a dielectric layer on said silicide layer andpositioned laterally immediately adjacent to said dielectric spaceropposite said lower portion and further positioned vertically betweensaid section of said silicide layer and said upper portion.
 3. Thetransistor of claim 1, said intrinsic base comprising any one ofepitaxial silicon and epitaxial silicon germanium.
 4. A transistorcomprising: an intrinsic base; an emitter on said intrinsic base, saidemitter comprising: a lower portion; and an upper portion above saidlower portion; a dielectric spacer positioned laterally adjacent to saidlower portion; an extrinsic base above said intrinsic base andpositioned laterally adjacent to said dielectric spacer opposite saidlower portion; and a silicide layer on said extrinsic base andpositioned laterally adjacent to said dielectric spacer opposite saidlower portion, said upper portion being wider than said lower portion,extending laterally over said dielectric spacer and a section of saidsilicide layer, and having a top surface and a tapered sidewall, saidtapered sidewall tapering from said top surface toward said dielectricspacer such that a width of said upper portion decreases between saidtop surface and an interface between said upper portion and said lowerportion.
 5. The transistor of claim 4, further comprising a dielectriclayer on said silicide layer and positioned laterally adjacent to saiddielectric spacer opposite said lower portion and further positionedvertically between said section of said silicide layer and said taperedsidewall of said upper portion.
 6. The transistor of claim 4, saidtapered sidewall having a taper angle ranging between 30 and 75 degrees.7. The transistor of claim 4, said tapered sidewall having a taper angleof approximately 45 degrees.
 8. The transistor of claim 4, said taperedsidewall being any one of linear and curved.
 9. The transistor of claim4, said intrinsic base comprising any one of epitaxial silicon andepitaxial silicon germanium.
 10. A heterojunction bipolar transistorcomprising: an intrinsic base comprising epitaxial silicon germanium; anemitter on said intrinsic base, said emitter comprising: a lowerportion; and an upper portion above said lower portion; a dielectricspacer positioned laterally adjacent to said lower portion; an extrinsicbase above said intrinsic base and positioned laterally adjacent to saiddielectric spacer opposite said lower portion; and a silicide layer onsaid extrinsic base and positioned laterally adjacent to said dielectricspacer opposite said lower portion, said upper portion being wider thansaid lower portion, extending laterally over said dielectric spacer anda section of said silicide layer, and having a top surface and a taperedsidewall, said tapered sidewall tapering from said top surface towardsaid dielectric spacer such that a width of said upper portion decreasesbetween said top surface and an interface between said upper portion andsaid lower portion.
 11. The transistor of claim 10, further comprising adielectric layer on said silicide layer and positioned laterallyadjacent to said dielectric spacer opposite said lower portion andfurther positioned vertically between said section of said silicidelayer and said tapered sidewall of said upper portion.
 12. Thetransistor of claim 10, said tapered sidewall having a taper angleranging between 30 and 75 degrees.
 13. The transistor of claim 10, saidtapered sidewall having a taper angle of approximately 45 degrees. 14.The transistor of claim 10, said tapered sidewall being any one oflinear and curved.
 15. A method of forming a transistor, said methodcomprising: performing at least one etch process so as to create, from apolysilicon layer, an emitter comprising: a lower portion and an upperportion above said lower portion, said lower portion being on anintrinsic base and positioned laterally adjacent to a dielectric spacerand said upper portion being wider than said lower portion and extendinglaterally over said dielectric spacer onto a sacrificial layer;selectively removing said sacrificial layer so as to expose an extrinsicbase on said intrinsic base and positioned laterally adjacent to saiddielectric spacer opposite said lower portion; and forming a silicidelayer on said extrinsic base such that said silicide layer is positionedlaterally adjacent to said dielectric spacer opposite said lower portionand such that a section of said silicide layer is below said upperportion.
 16. The method of claim 15, said forming of said silicide layercomprising: sputtering a metal layer onto said extrinsic base in orderto ensure that said metal layer is deposited below said upper portion ofsaid emitter, said sputtering being performed at a pressure of at least20 mTorr and with a radio frequency (RF) bias of at least 5 Watts; andperforming a silicidation anneal.
 17. The method of claim 15, furthercomprising forming a dielectric layer on said silicide layer such thatsaid dielectric layer is positioned laterally adjacent to saiddielectric spacer opposite said lower portion and further positionedvertically between said section of said silicide layer and said taperedsidewall of said upper portion.
 18. The method of claim 15, said formingof said intrinsic base comprising epitaxially growing, on a siliconsubstrate, any one of silicon layer and a silicon germanium layer.
 19. Amethod of forming a bipolar transistor, said method comprising:performing at least one etch process so as to create, from a polysiliconlayer, an emitter comprising: a lower portion and an upper portion abovesaid lower portion, said lower portion being on an intrinsic base andpositioned laterally adjacent to a dielectric spacer, and said upperportion being wider than said lower portion, extending laterally oversaid dielectric spacer onto a sacrificial layer and having a taperedsidewall, said tapered sidewall tapering from a top surface of saidupper portion toward said dielectric spacer such that a width of saidupper portion decreases between said top surface and an interfacebetween said upper portion and said lower portion; selectively removingsaid sacrificial layer so as to expose an extrinsic base on saidintrinsic base and positioned laterally adjacent to said dielectricspacer opposite said lower portion; and forming a silicide layer on saidextrinsic base such that said silicide layer is positioned laterallyadjacent to said dielectric spacer opposite said lower portion and suchthat a section of said silicide layer is below said upper portion. 20.The method of claim 19, said forming of said silicide layer comprising:sputtering a metal layer onto said extrinsic base in order to ensurethat said metal layer is deposited below said upper portion of saidemitter, said sputtering being performed at a pressure of at least 20mTorr and with a radio frequency (RF) bias of at least 5 Watts; andperforming a silicidation anneal.
 21. The method of claim 19, saidperforming of said at least one etch process comprising performing saidat least one etch process such that said tapered sidewall has a taperangle ranging between 30 and 75 degrees.
 22. The method of claim 19,said performing of said at least one etch process comprising performingsaid at least one etch process such that said tapered sidewall has ataper angle of approximately 45 degrees.
 23. The method of claim 19,said performing of said at least one etch process comprising performingsaid at least one etch process such that said tapered sidewall is anyone of linear and curved.
 24. The method of claim 19, further comprisingforming a dielectric layer on said silicide layer such that saiddielectric layer is positioned laterally adjacent to said dielectricspacer opposite said lower portion and further positioned verticallybetween said section of said silicide layer and said tapered sidewall ofsaid upper portion.
 25. The method of claim 19, said forming of saidintrinsic base comprising epitaxially growing, on a silicon substrate,any one of silicon layer and a silicon germanium layer.